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Κατηγορία

Περιοχή

Απασχόληση

Εταιρία:
u-blox Athens S.A
Ημερομηνία Δημοσίευσης:
01-07-20
Τύπος απασχόλησης:
Πλήρης
Κωδικός θέσης εργασίας:
Κατηγορία εργασίας:
Πληροφορική
Μηχανικοί
Περιοχή εργασίας:
Νομός Αττικής

IC Physical Design Engineer - Athens

Vacancy Name: IC Physical Design Engineer
Location City: Athens

Location Region: Attica
Location Country: Greece

Role also available in:

About u-blox u-blox (SIX:UBXN) is a global provider of leading positioning and wireless communication technologies for the automotive, industrial, and consumer markets. Our solutions let people, vehicles, and machines determine their precise position and communicate wirelessly over cellular and short range networks. With a broad portfolio of chips, modules, and a growing ecosystem of product supporting data services, u-blox is uniquely positioned to empower its customers to develop innovative solutions for the Internet of Things, quickly and cost-effectively. With headquarters in Thalwil, Switzerland, the company is globally present with offices in Europe, Asia, and the USA.

Job Description:

General Job Goals:

To support the development of next-generation SoCs in positioning, cellular and short-range applications, u-blox Athens is looking for an experienced IC Physical Design engineer. The ideal candidate needs to be creative, innovative, enthusiastic about new technologies, and striving for excellence. Moreover, (s)he has to present working experience in the topics of interest and be able to start contributing on real project tasks in short period. Through teamwork, training and dedication to personal development, u-blox goal is that every engineer quickly learns about different aspects of developing complex SoCs, starts developing to different project tasks, and eventually develops into a field expert.

Key responsibilities for the engineer will be to drive front-end and back-end implementation from RTL to gds2, including synthesis, floor-planning, P&R, netlist simulations, timing constraints, timing and power convergence, ECO implementation, memory and logic BIST, DfT logic generation/integration/physical hardening, validation DfT structural test pattern into full scale production, ATPG, test-coverage and pre/post silicon verification.

Your responsibilities:

  • Responsible for physical implementation aspects, such as: (physical)-synthesis, SDC, power-planning, CTS, floorplanning, P&R, STA, memory/logic BIST
  • Contribute to chip layout/physical design concepts, methodologies and flows (power IR, custom routing, pad ring, ECO implementation, etc)
  • Responsible for technology evaluation, considering DVS techniques, and advanced power reduction techniques
  • Executing static timing and crosstalk/noise analysis and timing closure concepts
  • Performing formal and physical verification (LVS/DRC)
  • Knowledge of DfT verification, IC test vector generation and IC testing and debugging flow
  • Responsible for clock domain crossing verification
  • Experience with Unix environment and shell programming/scripting (C-shell, Tcl, Perl, Python)
  • Familiar with high-level programming languages (C/C++)
  • Knowledge of SoC hardware components
  • Plan, track, and report for Physical implementation related tasks related to specific projects
  • Technical Documentation and reports (English language)
  • Familiar with mixed-signal designs
  • Provide input for and review data sheets, user guides and release notes

Qualifications

  • PhD/MS or BS in engineering with a focus on VLSI and specifically physical design and DfT
  • 3+ years experience in physical implementation and/or DfT related aspects
  • Good communications skills
  • Good knowledge in scripting languages
  • Strive for innovation and adoption of leading edge solutions
  • Used to and comfortable with team working
  • Used to work independently and precisely
  • Experience in commercial HDL design: Embedded CPU, bus-systems, peripherals, co-processors, memories, clock- and power-management, test and verification
  • Excellent skills in ASIC tools usage, e.g. Cadence, Modelsim, Synopsys
  • Experience in communication systems IP design: DSP, hardware accelerators, co-processors, dedicated IP
  • Experience in ICM, Perforce, and/or SVN version control is an advantage
  • Good English skills
  • Greek or EU or Schengen citizen or holder of a valid Greek work permit

Applications Close Date

Contact Are you interested in this challenging position within an international work environment in a successful company?

Apply now! You will be working with a motivated team in an exciting technology.

We are looking forward to receiving your application.

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